The invention relates to an ATM network comprising a data rate readjustment device for channels with input cells in the asynchronous time division technology (ATM virtual circuit), which channels are present at the input of a memory MC for cells and are constituted by separate digital lines or by an input multiplex carrier DNI, the said memory MC being formed by a plurality of r virtual circuit buffer memories, each cell of an activated channel being accommodated in that virtual circuit buffer memory whose identity is recognizable from the header of the said cell, while the output cells of the memory MC present on an output multiplex carrier DNO with a cell rate F are read from the said virtual circuit buffer memories by a readout address selection circuit.
The user of this device in the network may be a subscriber who has at his disposal a small number of channels, but advantageously it is the operator of a comparatively great number of virtual circuits, for example 128 or 256, established between several subscribers, in which case the device may be incorporated in a telecommunication exchange upstream of grading networks.
In an ATM transmission path, each cell of fixed length comprises a header which contains inter alia the identification number of the virtual circuit (or channel) to which it belongs. The header is followed by a message body which carries the useful information and has a fixed length. Such cells follow one another without interruption on the transmission line with a given fixed cadence which defines an appearance period T of the cell on the transmission line considered which will be referred to as cell time. The appearance rate of useful cells on the transmission line may vary. To safeguard the said regular period T when there is no message to be transmitted, a padding is provided in the form of empty cells of the same format as the useful cells, but carrying a standard, meaningless information. The same identification information is found in the headers of irregularly spaced cells which have the same destination.
The ATM transmission lines at the input side to be considered for the network according to the invention may be multiple, each of them constituting a single channel, may be arranged on a single multiplex carrier constituted by a single conductor or by several parallel conductors, or may be a combination of these two types of transmission line.
The envisaged aim, the problem to be resolved, is to rearrange the said input channels so that they are regrouped on an output multiplex carrier DNO, and to render the data rate of each of these channels regular, which data rates, which are generally different, are supposed to be known or which are at least measurable on the basis of an average appearance frequency of the cells. The data rates to be taken into account for the sources capable of feeding the various channels show a wide range of variation, which is indeed at present being standardized, and which may vary from a few kilobits per second (kb/s) to several hundreds of megabits per second (Mb/s). It is assumed for the ensuing description, moreover, that at least one of these data rates, referred to as the maximum channel data rate DCmax, is capable of exceeding half the maximum data rate F of the output multiplex carrier DNO. This means the presence of adjacent cells (in succession) on the multiplex DNO for such maximum data rates. By contrast, in the case of channel data rates DC such as DC&lt;F/2, for which the presence of adjacent cell groupings is not necessary, the invention renders it possible to avoid this type of grouping which is considered undesirable and to optimize the spacing regularity of the cells emitted through each channel, taking into account the presence of the other channels on the same multiplex.
French Patent Application 2 653 284 discloses a device for regulating the data rates of virtual circuits which use an ATM transmission line. In this device, command means are provided which are so operated that the cells to be transmitted through the output line are read in the buffer memories in a sequence such that the cells issued by one and the same virtual circuit buffer memory are spaced apart on average at least by an interval determined for this virtual circuit. To obtain the regulation of the data rates, the cited Application has recourse to a solution which essentially lies in the field of software and which does not render it possible to obtain high operating speeds, given the very high information data rates involved. This may lead to problems especially during system reconfigurations following a change in the state or the data rate of the activated channels.